1. Field of the Invention
The present invention relates to a digital pulse processing device suitable for use to preprocess a detection signal representing the speed of a moving or rotating body before it is supplied to a digital motor speed control device.
2. Description of the Related Art
The pulse processing function of conventional speed detection devices is disclosed in, for example, Japanese Patent Laid-open No. Sho59-100866. This pulse processing function of the speed detection device includes a first counter A for counting a pulse train output from a pulse generator, a second counter B for counting clock pulses having a fixed higher frequency than the pulse train, and a latch for storing the count of the second counter B. This speed detection device is implemented by hardware designed to store the counted value of the clock pulses of the second counter B each time a pulse is output from the pulse generator.
In the above-described speed detecting device, counting of the pulses from the pulse generator and counting of clock pulses are synchronized so as to achieve accurate speed detection. The speed detection operation carried out is to obtain a speed detection value Nt by executing the following expression using the pulse counted value A (i) of the first counter A, a latched value B (i) of the second counter B, the values A and B being obtained at the present reading in of a microcomputer, and the values A (i-1) and B (i-1) obtained by the previous reading in of the microcomputer: ##EQU1## where K is a constant, .DELTA.A is a change in the first counter A, and .DELTA.B is a change in the second counter B.
When the motor is rotating at a low speed, the pulse width of the pulses output from the pulse generator is large, and the counted value of the pulses may not change in the microcomputer's reading-in intervals which is generally several msec. At that time, .DELTA.A (i)=1, and .DELTA.B (i)=0, and the speed detection operation is impossible.
To overcome this problem, in the aforementioned conventional technique, a RD (read) signal is output from the microcomputer by the software. When the speed detecting device receives this RD signal, it forcibly stores the counted value of the clock pulses in the latch asynchronously with the counting of the pulse output device. In that case, the speed detection operation is executed using the previously obtained values of .DELTA.A (i) and .DELTA.B (i) obtained by subtracting the previously obtained clock pulses counted value from the clock pulses counted values latched by the RD signal.
Regarding a subsequent reading-in of the microcomputer, if no pulse is output from the pulse output device, .DELTA.A (i) is that used in the previous operation, and .DELTA.B (i) is the value obtained by adding to the previous .DELTA.B (i) the value obtained by subtracting the previously read in clock pulse counted value from the clock pulse counted value latched by the RD signal. Therefore, .DELTA.B (i) is the value obtained between the last pulse output from the pulse generator and the present reading-in presently read value of the microcomputer.
In the aforementioned conventional technique, when .DELTA.A (i)=0, the speed detection operation requires complicated processings, the such as branch processing, output of a RD signal and cumulative addition of .DELTA.B (i), which increase the burden on the software.
Furthermore, no consideration is given to the precision of the latch for storing the counted values A (i) and B (i) of the counter for counting the pulses of the pulse generator and the counter for counting the clock pulses. That is, since the number of bits for the latch is fixed, the precision is also fixed. Consequently, a higher precision than required is obtained for a certain application, while an insufficient precision is obtained for another application. As a result, the conventional latching is not versatile, and pulse processing cannot be achieved over a wide range of precision.
Furthermore, no consideration is given to the overflow of the counter B (i) for counting the clock pulses. That is, although .DELTA.B (i) can be obtained when an overflow condition occurs in the counter B (i) once, if an overflow condition occurs more than once, it is impossible to obtain an accurate .DELTA.B (i) because there is no function of checking the number of times the overflow condition occurs. This makes accurate speed detection impossible.